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Hardware Architecture

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Total of 67 entries : 1-50 51-67
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Mon, 12 Oct 2026 (showing 10 of 10 entries )

[1] arXiv:2610.13498 [pdf, html, other]
Title: A Hybrid and Hierarchical Ray Tracing Method for Efficient 3D Gaussian Rendering
Tiancheng Zhao, Sixu Li, Yuzhou Chen, Hengyu Ding, Zhiming Pan, Chaojian Li
Subjects: Hardware Architecture (cs.AR); Graphics (cs.GR)
[2] arXiv:2610.13368 [pdf, html, other]
Title: Anechoic: Onsager-Corrected Parallel Annealing for Sub-0.1 ms Dense Max-Cut on an FPGA
Seungki Hong, Kyeongwon Jeong, Taekwang Jang
Subjects: Hardware Architecture (cs.AR)
[3] arXiv:2610.13320 [pdf, html, other]
Title: Hardware-in-the-Loop Demo of a Cooperative Intersection where Cars don't Stop
Lorenzo Farina, Matteo Piccoli, Salvatore Iandolo, Antonio Solida, Carlo Augusto Grazia, Marco Rapelli, Francesco Raviglione, Claudio Casetti, Alessandro Bazzi
Comments: 3 pages, 3 figures, accepted at IEEE CSCN 2025
Subjects: Hardware Architecture (cs.AR)
[4] arXiv:2610.13067 [pdf, html, other]
Title: TPCS: A Cycle-Level Simulation Paradigm with Native Execution Semantics for RTL Modeling and Generation
Chengzhen Meng, Xiaoyu Li, Chen Bai, Zhenyu Zhang, Hongjun Dai
Comments: Submitted to IEEE TC
Subjects: Hardware Architecture (cs.AR)
[5] arXiv:2610.12940 [pdf, html, other]
Title: CacheFlex: Direct Software-Managed Access to Higher-Level Cache for Scalable Vector Support
Jingqun Zhang, Maohua Nie, Jiayi Wang, Weihang Li, Rishi Sappidi, Shwet Chitnis, Ang Li
Comments: To appear in MICRO 2026. 15 pages, 9 figures, 4 tables
Subjects: Hardware Architecture (cs.AR)
[6] arXiv:2610.12661 [pdf, html, other]
Title: VortexSynth: Profile-guided benchmark reconstruction for GPU architecture research
Huanzhi Pu, Chulhyung Park, Chihyo Ahn, Ramyad Hadidi, Hyesoon Kim
Comments: 14 pages, 6 figures
Subjects: Hardware Architecture (cs.AR); Programming Languages (cs.PL)
[7] arXiv:2610.13843 (cross-list from quant-ph) [pdf, html, other]
Title: A Hardware-Native Trapped-Ion Hybrid Qudit-Oscillator Instruction Set
Masoud Hakimi Heris, Yuan Liu, Frank Mueller
Comments: 27 pages, 10 figures, 10 tables. Submitted to ACM Transactions on Quantum Computing
Subjects: Quantum Physics (quant-ph); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)
[8] arXiv:2610.13125 (cross-list from cs.OS) [pdf, html, other]
Title: Characterizing CPU-GPU Memory Sharing over Unified Memory Architecture
Jinrong Yang, Zimeng Wang, Rong Chen, Haibo Chen
Comments: Accepted to EuroSys 2027. 22 pages, 21 figures
Subjects: Operating Systems (cs.OS); Hardware Architecture (cs.AR)
[9] arXiv:2610.12795 (cross-list from cs.CR) [pdf, html, other]
Title: Power, Performance, and Area of HPC-Based Malware Detectors: An FPGA and Open-PDK ASIC Study
Alireza Abolhasani Zeraatkar, Parnian Shabani Kamran, Parsa Mirfasihi, Saleh Khalaj Monfared, Hussain Al-Asaad
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[10] arXiv:2607.03148 (cross-list from cs.LG) [pdf, html, other]
Title: Rethinking Neural Nonlinearity as Gating
Muhammad Sabih, Frank Hannig, Jürgen Teich
Subjects: Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)

Fri, 9 Oct 2026 (showing 9 of 9 entries )

[11] arXiv:2610.11748 [pdf, html, other]
Title: DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference
Yousef Sadegheih, Dorit Merhof, Muhammad Usman
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
[12] arXiv:2610.11284 [pdf, html, other]
Title: DynaTE: Accelerating Diffusion LLMs via Dynamic Token Execution
Minghan Jiang, Jiayi Wang, Shuaiting Li, Haibin Shen, Kejie Huang
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[13] arXiv:2610.10985 [pdf, html, other]
Title: ATLAS: Adaptive TDA-guided Landscape-Aware Transistor Sizing
Youngmin Oh, Jihwan Won, Yuntae Park, Bosun Hwang, Suwan Kim
Subjects: Hardware Architecture (cs.AR)
[14] arXiv:2610.10924 [pdf, html, other]
Title: The Missing Fourth Term for the Emulation Tensor Memory Equilibrium (TME) Model: The Residue Deconstruction Cost
Harun Bayraktar, John Gunnels, Peter Caday
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Performance (cs.PF)
[15] arXiv:2610.10858 [pdf, html, other]
Title: RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design
Awani Khodkumbhe, Yunfei Feng, Raj Rangarajan, Kevin Wang, Kamal Sahota
Comments: 6 pages, 4 figures. Submitted to ACM/IEEE for possible publication
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG); Multiagent Systems (cs.MA); Systems and Control (eess.SY)
[16] arXiv:2610.10580 [pdf, html, other]
Title: A Survey on LLM-Integrated Hardware Design Verification
Hao Zheng, Jaime Rafael Imperial, Bardia Nadimi, Xiangfei Kong
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Software Engineering (cs.SE)
[17] arXiv:2610.10579 [pdf, html, other]
Title: CacheFit: The Rising Cost of Cache Replacement and Constraint-Driven Redesign of Last-Level Cache Replacement Policies
Bita Aslrousta, Kaushal Mhapsekar, Darsh Asher, Azam Ghanbari, Joshua Kalyanapu, Samira Mirbagher Ajorpaz
Subjects: Hardware Architecture (cs.AR); Performance (cs.PF)
[18] arXiv:2610.10544 [pdf, html, other]
Title: A Modular Event-Driven Software Architecture for Open-Source Industrial IoT Edge Gateways
Pei Yu Wong, Thien Tran, Hudyjaya Siswoyo Jo, Jonathan Kua
Comments: 4 pages, 3 figures, 1 table, 1 function, accepted paper on the 24th IEEE International Conference on Industrial Informatics (INDIN), 26-29 July, 2026, Melbourne, Australia
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC); Systems and Control (eess.SY)
[19] arXiv:2610.11447 (cross-list from cs.SE) [pdf, html, other]
Title: Closed-loop evaluation of LLM agents for embedded software development
Jorge García-Carrasco, Sergio García-Carrasco, Alejandro Maté, Juan Trujillo
Comments: Published in Journal of Systems Architecture 179 (2026) 103937. 23 pages, 4 figures, 5 tables. Code and artifacts: this https URL
Journal-ref: J. Syst. Archit. 179 (2026) 103937
Subjects: Software Engineering (cs.SE); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Machine Learning (cs.LG)

Thu, 8 Oct 2026 (showing 8 of 8 entries )

[20] arXiv:2610.10403 [pdf, html, other]
Title: SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS
Lennart Van Hirtum, David Volz, Andreas Koch, Christian Plessl
Comments: Accepted at the International Conference on Field-Programmable Technology (FPT) 2026. 9 pages, 9 figures
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC)
[21] arXiv:2610.10129 [pdf, html, other]
Title: When Algorithmic Exploration Becomes Cheap: A Case Study of Agentic Research in EDA
Keren Zhu, Yu Deng, Xiaoyu Hao, Liwen Jiang, Zijian Jiang, Cunqing Lan, Boxiang Song, Pujun Su, Yaojia Wang
Comments: 12 pages, 10 figures
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[22] arXiv:2610.09999 [pdf, html, other]
Title: ReSAFT: An Efficient Stuck-at Fault-Tolerant Scheme for ReRAM-based Process-in-Memory Accelerators
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi
Journal-ref: Dorostkar, Aniseh, Hamed Farbeh, and Hamid R. Zarandi. "ReSAFT: An efficient stuck-at fault-tolerant scheme for ReRAM-based process-in-memory accelerators." Future Generation Computer Systems 185 (2026): 108685
Subjects: Hardware Architecture (cs.AR)
[23] arXiv:2610.09447 [pdf, html, other]
Title: BenchmarkAnything: Agent-Driven Construction of Simulator-Ready Microarchitecture Benchmarks
Xiangfeng Sun, Ceyu Xu, Chen Bai, Yuan Xie
Subjects: Hardware Architecture (cs.AR)
[24] arXiv:2610.09292 [pdf, html, other]
Title: An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
Jun Zhang, Weizhi Bian, Hao Zhang
Subjects: Hardware Architecture (cs.AR)
[25] arXiv:2610.09156 [pdf, html, other]
Title: Compiling Semi-Ring Dynamic Programming to Tier-Aware 3D-DRAM Processing-in-Memory
Mahbod Afarin, Tsung-Han Lu, Tajana Rosing
Subjects: Hardware Architecture (cs.AR)
[26] arXiv:2610.10311 (cross-list from cs.LG) [pdf, html, other]
Title: Fault-tolerant foundation models
Trevor McCourt, Ila R. Fiete, Isaac L. Chuang
Subjects: Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)
[27] arXiv:2610.08899 (cross-list from cs.PF) [pdf, html, other]
Title: CXDVirt: Low Latency Kernel Module Based CXL-SSD Emulation
Hyunsun Chung, Seongho Bong, Hong-Yeon Kim, Youngjae Kim
Comments: 6 pages, 8 figures. To be presented at the 17th International Workshop on Performance Modeling, Benchmarking and Simulation of High Performance Computer Systems (PMBS), held in conjunction with SC26
Subjects: Performance (cs.PF); Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)

Wed, 7 Oct 2026 (showing first 23 of 26 entries )

[28] arXiv:2610.08688 [pdf, html, other]
Title: A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
Ajay Kumar M, Vishnu PS, Yike Li, Shreejith Shanker, Dimitrios S. Nikolopoulos, Bo Ji, Hans Vandierendonck, Deepu John
Comments: Accepted for publication at the 2026 IEEE 33rd International Conference on Electronics, Circuits and Systems (ICECS)
Subjects: Hardware Architecture (cs.AR)
[29] arXiv:2610.08502 [pdf, html, other]
Title: X-OPM: Explainable Automatic Digital On-Chip Power Modeling for Enhanced Robustness
Jingbo Jiang, Xizi Chen, Jian Peng, Wei Zhang
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
[30] arXiv:2610.08483 [pdf, html, other]
Title: Trail: Scalable and Low-Cost Temporal TLB Prefetching via Page-Table-Embedded Deltas
Konstantinos Kanellopoulos, Konstantinos Sgouras, Harsh Songara, Rahul Bera, Onur Mutlu
Subjects: Hardware Architecture (cs.AR); Operating Systems (cs.OS); Performance (cs.PF)
[31] arXiv:2610.08378 [pdf, html, other]
Title: Lachesis: Lifetime-Aware KV Cache Placement for Agent Serving across HBM and High-Bandwidth Flash
Jaehoon Yang, Jeongmin Lee, Haneul Park, Seung Yul Lee, Nam Sung Kim, Jae W. Lee
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC)
[32] arXiv:2610.08373 [pdf, html, other]
Title: ECO: Energy-Oriented Configuration Optimization for Attention FFN Disaggregated LLM Serving
Zou Qingyun, Bin Gao, Zhuobin Huang, Weng-Fai Wong, Tulika Mitra, Bingsheng He
Subjects: Hardware Architecture (cs.AR)
[33] arXiv:2610.08190 [pdf, html, other]
Title: On the Impact of Degradation-Balanced Scheduling in Manycore Systems
Maria Pantazi-Kypraiou, George Goudroumanis, George Floros, Anuj Pathania, George Stamoulis
Comments: Accepted at ICECS 2026
Subjects: Hardware Architecture (cs.AR)
[34] arXiv:2610.08186 [pdf, html, other]
Title: A gem5-based Simulation Framework for Computing-in-DRAM
Alexander Kusnezoff, João Paulo C. de Lima, Jeronimo Castrillon, Asif Ali Khan
Comments: 8 pages, 4 figures, 4 tables
Subjects: Hardware Architecture (cs.AR); Emerging Technologies (cs.ET)
[35] arXiv:2610.07685 [pdf, html, other]
Title: CHiRP: Control-Flow History Reuse Prediction
Samira Mirbagher-Ajorpaz, Elba Garza, Gilles Pokam, Daniel A. Jiménez
Comments: Author manuscript of MICRO 2020. 15 manuscript pages plus publication-notice page
Journal-ref: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 131-145 (2020)
Subjects: Hardware Architecture (cs.AR)
[36] arXiv:2610.07668 [pdf, html, other]
Title: CACHEFORGE: LLM-Guided End-to-End Generative Cache Replacement Policy for Performance and Hardware Efficiency
Kaushal Mhapsekar, Bita Aslrousta, Brijesh Kumar Bhayana, Paula Contreras, Azam Ghanbari, Ethan Goodman, Anna Andriiko, Samira Mirbagher Ajorpaz
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG)
[37] arXiv:2610.07600 [pdf, html, other]
Title: Beyond No-Good Benders Cuts: Exact Realizability for Discretely Tunable Clock Trees
Boxiang Song, Keren Zhu
Subjects: Hardware Architecture (cs.AR)
[38] arXiv:2610.07443 [pdf, html, other]
Title: A Shape-Adaptive Architecture with Disaggregated Quantization for Efficient LLM Serving
Cong Guo, Chiyue Wei, Bowen Duan, Haoxuan Shan, Benjamin F. Morris III, Yintao He, Hai "Helen" Li, Yiran Chen
Comments: 14 pages, 14 figures, 4 tables
Subjects: Hardware Architecture (cs.AR)
[39] arXiv:2610.07301 [pdf, html, other]
Title: A Pipelined FPGA Architecture for Banded Sparse Matrix Dense Matrix Multiplication in Longformer
Phillip Pramberger, Athanasios Tziouvaras, Shreejith Shanker, George Floros
Comments: Accepted at ICECS 2026
Subjects: Hardware Architecture (cs.AR)
[40] arXiv:2610.07191 [pdf, html, other]
Title: Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
Geetha Prasuna Yarramneni, Surya Selvam, Wilfried Haensch, Anand Raghunathan
Comments: Published at the 2026 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD '26), Jeju Island, Republic of Korea, September 7-9, 2026
Journal-ref: Proceedings of the 2026 ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD '26), September 7-9, 2026, Jeju Island, Republic of Korea. ACM, New York, NY, USA, 8 pages
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[41] arXiv:2610.07094 [pdf, html, other]
Title: Evaluating Inference Compute for Generative AI: A Framework for Enterprise Workloads
Abbas Raza Ali, Muhammad Ajmal Siddiqui, Moona Zahid
Subjects: Hardware Architecture (cs.AR); Distributed, Parallel, and Cluster Computing (cs.DC); Machine Learning (cs.LG); Performance (cs.PF)
[42] arXiv:2610.07078 [pdf, html, other]
Title: SVRF: Efficient Register Storage for Long-Vector Architectures
Francesco Minervini, Lorenzo Deltetto, Osman Unsal, Adrian Cristal
Subjects: Hardware Architecture (cs.AR)
[43] arXiv:2610.07029 [pdf, html, other]
Title: An Empirical Fault Vulnerability Exploration of ReRAM-based Process-in-Memory CNN Accelerators
Aniseh Dorostkar, Hamed Farbeh, Hamid R. Zarandi
Journal-ref: A. Dorostkar, H. Farbeh and H. R. Zarandi, "An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators," in IEEE Transactions on Reliability, vol. 74, no. 1, pp. 2290-2304, March 2025
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
[44] arXiv:2610.06937 [pdf, html, other]
Title: FAPO: Fanout-Aware Post-Mapping Optimization for LUT-Based FPGAs
Xiaoyu Hao, Keren Zhu
Subjects: Hardware Architecture (cs.AR)
[45] arXiv:2610.06905 [pdf, html, other]
Title: ElecSafety: Diagnosing Large Language Model Safety Judgments for Microcontroller Boards
Linjian Yang, Xinyan Wang, Kunpeng Liu
Subjects: Hardware Architecture (cs.AR)
[46] arXiv:2610.08457 (cross-list from cs.LG) [pdf, html, other]
Title: Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction
Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang, Didier Chételat, Yingxue Zhang
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR)
[47] arXiv:2610.08444 (cross-list from cs.RO) [pdf, html, other]
Title: ActTune: Action-Aware Precision and GPU Operating-Point Adaptation for Energy-Efficient Vision-Language-Action Inference
Zou Qingyun, Bin Gao, Wenju Zhao, Weng-Fai Wong, Bingsheng He, Tulika Mitra
Subjects: Robotics (cs.RO); Hardware Architecture (cs.AR)
[48] arXiv:2610.08372 (cross-list from cs.DC) [pdf, html, other]
Title: vTen: Tensor-Centric Verification Framework for Domain-Specific Accelerators
Chanmin Baek, Keehyuk Lee, Mincheol Cha, Somi Hong, Xuan Truong Nguyen, Hyuk-Jae Lee
Comments: 7 pages, 8 figures, 1 table. Accepted at the 63rd ACM/IEEE Design Automation Conference (DAC '26), Long Beach, CA, USA
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR)
[49] arXiv:2610.08301 (cross-list from cs.CR) [pdf, html, other]
Title: Zeppelin: Client-Side BFV Encryption and Decryption for Helium-Powered Microcontrollers
Muhammad Saif ul Islam, Karar Haider, Manaal Malik, Naveed Anwar Bhatti, Muhammad Ali Siddiqi
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
[50] arXiv:2610.07820 (cross-list from cs.CR) [pdf, html, other]
Title: Efficient and Implementation-Hardened RBLWE on Commodity Cortex-M Microcontrollers
Muhammad Asim Javaid, Muhammad Adeel Pasha, Muhammad Ali Siddiqi
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
Total of 67 entries : 1-50 51-67
Showing up to 50 entries per page: fewer | more | all